Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design

Bharat Sukhwani, Uday Padmanabhan, Janet M. Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's sealing limitations. However, many such devices exhibit nonmonotonie I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Pages758-763
Number of pages6
DOIs
StatePublished - Dec 1 2005
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
VolumeII
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

ASJC Scopus subject areas

  • Engineering(all)

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    Sukhwani, B., Padmanabhan, U., & Wang, J. M. (2005). Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design. In Proceedings - Design, Automation and Test in Europe, DATE '05 (pp. 758-763). [1395669] (Proceedings -Design, Automation and Test in Europe, DATE '05; Vol. II). https://doi.org/10.1109/DATE.2005.221