Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design

Bharat Sukhwani, Uday Padmanabhan, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's sealing limitations. However, many such devices exhibit nonmonotonie I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE '05
Pages758-763
Number of pages6
VolumeII
DOIs
StatePublished - 2005
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

Fingerprint

Nanotechnology
Simulators
Networks (circuits)
Circuit simulation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sukhwani, B., Padmanabhan, U., & Wang, M. (2005). Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design. In Proceedings -Design, Automation and Test in Europe, DATE '05 (Vol. II, pp. 758-763). [1395669] https://doi.org/10.1109/DATE.2005.221

Nano-sim : A step wise equivalent conductance based statistical simulator for nanotechnology circuit design. / Sukhwani, Bharat; Padmanabhan, Uday; Wang, Meiling.

Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. II 2005. p. 758-763 1395669.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sukhwani, B, Padmanabhan, U & Wang, M 2005, Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design. in Proceedings -Design, Automation and Test in Europe, DATE '05. vol. II, 1395669, pp. 758-763, Design, Automation and Test in Europe, DATE '05, Munich, Germany, 3/7/05. https://doi.org/10.1109/DATE.2005.221
Sukhwani B, Padmanabhan U, Wang M. Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design. In Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. II. 2005. p. 758-763. 1395669 https://doi.org/10.1109/DATE.2005.221
Sukhwani, Bharat ; Padmanabhan, Uday ; Wang, Meiling. / Nano-sim : A step wise equivalent conductance based statistical simulator for nanotechnology circuit design. Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. II 2005. pp. 758-763
@inproceedings{e9b10a5c5cbc402781ce0b0cbfe04ec4,
title = "Nano-sim: A step wise equivalent conductance based statistical simulator for nanotechnology circuit design",
abstract = "New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's sealing limitations. However, many such devices exhibit nonmonotonie I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.",
author = "Bharat Sukhwani and Uday Padmanabhan and Meiling Wang",
year = "2005",
doi = "10.1109/DATE.2005.221",
language = "English (US)",
isbn = "0769522882",
volume = "II",
pages = "758--763",
booktitle = "Proceedings -Design, Automation and Test in Europe, DATE '05",

}

TY - GEN

T1 - Nano-sim

T2 - A step wise equivalent conductance based statistical simulator for nanotechnology circuit design

AU - Sukhwani, Bharat

AU - Padmanabhan, Uday

AU - Wang, Meiling

PY - 2005

Y1 - 2005

N2 - New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's sealing limitations. However, many such devices exhibit nonmonotonie I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.

AB - New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's sealing limitations. However, many such devices exhibit nonmonotonie I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.

UR - http://www.scopus.com/inward/record.url?scp=33646933792&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646933792&partnerID=8YFLogxK

U2 - 10.1109/DATE.2005.221

DO - 10.1109/DATE.2005.221

M3 - Conference contribution

AN - SCOPUS:33646933792

SN - 0769522882

SN - 9780769522883

VL - II

SP - 758

EP - 763

BT - Proceedings -Design, Automation and Test in Europe, DATE '05

ER -