FPGA CAD requires routability driven algorithms to improve feasibility of mapping designs onto the underlying architecture. At the clustering stage, routability enhancing parameters such as number of absorbed pins, absorbed nets, criticality, connectivity, and number of net terminals have been identified. We argue that net length is an important parameter not explored in this context. In this paper, we show a structural approach to predict individual net lengths based on the Intrinsic Shortest Path Length (ISPL) metric, and use it to reduce track count achieved by previous clustering algorithms. For the set of 20 large MCNC benchmarks, we achieve an average channel width reduction of 3.25 tracks with no area overhead compared to previous approaches. The prediction mechanism and modified clustering algorithm have been incorporated into the VPack/VPR (Versatile Place and Route) toolset. This is a first approach that applies apriori net length predictions within the clustering stage to optimize a design for routability.