New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation

Ahmed Louri, Hongki Sung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provide more cacheability than the previous complier-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.

Original languageEnglish (US)
Title of host publicationProceedings of the Ninth Annual International Symposium on Computer Architecture
PublisherPubl by ACM
Pages428
Number of pages1
ISBN (Print)0897915097
StatePublished - 1993
EventProceedings of the 19th Annual International Symposium on Compu- ter Architecture - Gold Coast, Aust
Duration: May 19 1992May 21 1992

Other

OtherProceedings of the 19th Annual International Symposium on Compu- ter Architecture
CityGold Coast, Aust
Period5/19/925/21/92

Fingerprint

Storage allocation (computer)
Flow graphs
Data storage equipment

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Louri, A., & Sung, H. (1993). New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. In Proceedings of the Ninth Annual International Symposium on Computer Architecture (pp. 428). Publ by ACM.

New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. / Louri, Ahmed; Sung, Hongki.

Proceedings of the Ninth Annual International Symposium on Computer Architecture. Publ by ACM, 1993. p. 428.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Louri, A & Sung, H 1993, New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. in Proceedings of the Ninth Annual International Symposium on Computer Architecture. Publ by ACM, pp. 428, Proceedings of the 19th Annual International Symposium on Compu- ter Architecture, Gold Coast, Aust, 5/19/92.
Louri A, Sung H. New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. In Proceedings of the Ninth Annual International Symposium on Computer Architecture. Publ by ACM. 1993. p. 428
Louri, Ahmed ; Sung, Hongki. / New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. Proceedings of the Ninth Annual International Symposium on Computer Architecture. Publ by ACM, 1993. pp. 428
@inproceedings{de3efa2a17fe441fb558c36f900d71b0,
title = "New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation",
abstract = "We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provide more cacheability than the previous complier-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.",
author = "Ahmed Louri and Hongki Sung",
year = "1993",
language = "English (US)",
isbn = "0897915097",
pages = "428",
booktitle = "Proceedings of the Ninth Annual International Symposium on Computer Architecture",
publisher = "Publ by ACM",

}

TY - GEN

T1 - New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation

AU - Louri, Ahmed

AU - Sung, Hongki

PY - 1993

Y1 - 1993

N2 - We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provide more cacheability than the previous complier-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.

AB - We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provide more cacheability than the previous complier-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.

UR - http://www.scopus.com/inward/record.url?scp=0027849407&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027849407&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027849407

SN - 0897915097

SP - 428

BT - Proceedings of the Ninth Annual International Symposium on Computer Architecture

PB - Publ by ACM

ER -