New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation

Ahmed Louri, Hongki Sung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits non-stale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provide more cacheability than the previous complier-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes is also proposed.

Original languageEnglish (US)
Title of host publicationProceedings of the Ninth Annual International Symposium on Computer Architecture
PublisherPubl by ACM
Number of pages1
ISBN (Print)0897915097
StatePublished - Dec 1 1993
EventProceedings of the 19th Annual International Symposium on Compu- ter Architecture - Gold Coast, Aust
Duration: May 19 1992May 21 1992

Publication series

NameProceedings of the Ninth Annual International Symposium on Computer Architecture

Other

OtherProceedings of the 19th Annual International Symposium on Compu- ter Architecture
CityGold Coast, Aust
Period5/19/925/21/92

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Louri, A., & Sung, H. (1993). New complier-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. In Proceedings of the Ninth Annual International Symposium on Computer Architecture (Proceedings of the Ninth Annual International Symposium on Computer Architecture). Publ by ACM.