On the design of optimal fault - Tolerant systolic array architectures

M. O. Esonu, A. J. Al-Khalili, S. Hariri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present a novel approach for designing highly reliable and optimal fault - tolerant systolic array architectures. In our approach, fault - tolerant algorithms are designed by introducing redundant computations at the algorithmic level, so that when these algorithms are mapped into specific VLSI systolic array architectures, the architectures will be inherently fault - tolerant. We introduce redundant computations in the original algorithm by creating different versions of the algorithm. The respective dependency matrix (D) of the different versions of the algorithm are obtained and these are merged to give one dependency matrix that reflects a given fault - tolerant requirement. This resultant dependency matrix is mapped into an optimal fault - tolerant systolic array using our proposed Space - Time (S-T) systematic approach for mapping algorithms into optimal systolic architectures.

Original languageEnglish (US)
Title of host publicationProceedings - 5th International Parallel Processing Symposium, IPPS 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages352-357
Number of pages6
ISBN (Electronic)0818691670, 9780818691676
DOIs
StatePublished - Jan 1 1991
Externally publishedYes
Event5th International Parallel Processing Symposium, IPPS 1991 - Anaheim, United States
Duration: Apr 30 1991May 2 1991

Publication series

NameProceedings - 5th International Parallel Processing Symposium, IPPS 1991

Conference

Conference5th International Parallel Processing Symposium, IPPS 1991
CountryUnited States
CityAnaheim
Period4/30/915/2/91

ASJC Scopus subject areas

  • Computational Mathematics
  • Hardware and Architecture
  • Artificial Intelligence
  • Computer Networks and Communications
  • Computer Science Applications

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  • Cite this

    Esonu, M. O., Al-Khalili, A. J., & Hariri, S. (1991). On the design of optimal fault - Tolerant systolic array architectures. In Proceedings - 5th International Parallel Processing Symposium, IPPS 1991 (pp. 352-357). [153802] (Proceedings - 5th International Parallel Processing Symposium, IPPS 1991). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPPS.1991.153802