Optical and electronic error correction schemes for highly parallel access memories

Mark A. Neifeld, Jerry D. Hayes

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

We have fabricated and tested an optically addressed, parallel electronic Reed-Solomon decoder for use with parallel access optical memories. A comparison with various serial implementations has demonstrated that for many instances of code block size and error correction capability, the parallel approach is superior from the perspectives of VLSI layout area and decoding latency. The demonstrated [15,9] Reed-Solomon parallel pipeline decoder operates on 60 bit input words and has been demonstrated at a clock rate of 5MHz yielding a demonstrated data rate of 300Mbps.

Original languageEnglish (US)
Pages (from-to)543-553
Number of pages11
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume2026
DOIs
StatePublished - Nov 9 1993
EventPhotonics for Processors, Neural Networks, and Memories 1993 - San Diego, United States
Duration: Jul 11 1993Jul 16 1993

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

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