Parallel optical interconnection network for address transactions in large-scale cache coherent symmetric multiprocessors

Ahmed Louri, Avinash Karanth Kodi

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10%-67% improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85% better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.

Original languageEnglish (US)
Pages (from-to)667-676
Number of pages10
JournalIEEE Journal on Selected Topics in Quantum Electronics
Volume9
Issue number2
DOIs
StatePublished - Mar 2003

Fingerprint

Optical interconnects
Fiber optic networks
Bandwidth
central processing units
bandwidth
Optical devices
Bit error rate
Pipelines
bit error rate
exclusion
Data storage equipment
budgets
set theory
insertion
simulation

Keywords

  • Cache coherence
  • Parallel optical interconnects
  • Scalable optical networks
  • Symmetric multiprocessors (SMPs)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Atomic and Molecular Physics, and Optics

Cite this

@article{da88837230024efc82f91ea3d5a04e69,
title = "Parallel optical interconnection network for address transactions in large-scale cache coherent symmetric multiprocessors",
abstract = "The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10{\%}-67{\%} improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85{\%} better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.",
keywords = "Cache coherence, Parallel optical interconnects, Scalable optical networks, Symmetric multiprocessors (SMPs)",
author = "Ahmed Louri and Kodi, {Avinash Karanth}",
year = "2003",
month = "3",
doi = "10.1109/JSTQE.2003.814189",
language = "English (US)",
volume = "9",
pages = "667--676",
journal = "IEEE Journal of Selected Topics in Quantum Electronics",
issn = "1077-260X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

TY - JOUR

T1 - Parallel optical interconnection network for address transactions in large-scale cache coherent symmetric multiprocessors

AU - Louri, Ahmed

AU - Kodi, Avinash Karanth

PY - 2003/3

Y1 - 2003/3

N2 - The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10%-67% improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85% better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.

AB - The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10%-67% improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85% better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.

KW - Cache coherence

KW - Parallel optical interconnects

KW - Scalable optical networks

KW - Symmetric multiprocessors (SMPs)

UR - http://www.scopus.com/inward/record.url?scp=0242661455&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0242661455&partnerID=8YFLogxK

U2 - 10.1109/JSTQE.2003.814189

DO - 10.1109/JSTQE.2003.814189

M3 - Article

AN - SCOPUS:0242661455

VL - 9

SP - 667

EP - 676

JO - IEEE Journal of Selected Topics in Quantum Electronics

JF - IEEE Journal of Selected Topics in Quantum Electronics

SN - 1077-260X

IS - 2

ER -