Parameter reduction for variability analysis by slice inverse regression method

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

With semiconductor fabrication technologies that have scaled below 100nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation integrated circuit (IC) design. One of the biggest challenges is the enormous number of process-variation-related parameters. These parameters represent numerous local and global variations and pose a heavy burden in today's chip verification and design processes. A new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance is proposed. The new approach creates an effective reduction subspace and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which variability analysis is processed. Thus, the computational cost because of the number of variations is greatly reduced. Experimental results show that by using the new method, 20-50 parameter reduction with only <5 error on average can be achieved.

Original languageEnglish (US)
Pages (from-to)16-22
Number of pages7
JournalIET Circuits, Devices and Systems
Volume2
Issue number1
DOIs
StatePublished - 2008

Fingerprint

Semiconductor materials
Fabrication
Networks (circuits)
Costs
Integrated circuit design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Control and Systems Engineering

Cite this

Parameter reduction for variability analysis by slice inverse regression method. / Mitev, A.; Marefat, Michael Mahmoud; Ma, D.; Wang, Meiling.

In: IET Circuits, Devices and Systems, Vol. 2, No. 1, 2008, p. 16-22.

Research output: Contribution to journalArticle

@article{7ead260e0f1b49df93082a519c2b51bd,
title = "Parameter reduction for variability analysis by slice inverse regression method",
abstract = "With semiconductor fabrication technologies that have scaled below 100nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation integrated circuit (IC) design. One of the biggest challenges is the enormous number of process-variation-related parameters. These parameters represent numerous local and global variations and pose a heavy burden in today's chip verification and design processes. A new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance is proposed. The new approach creates an effective reduction subspace and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which variability analysis is processed. Thus, the computational cost because of the number of variations is greatly reduced. Experimental results show that by using the new method, 20-50 parameter reduction with only <5 error on average can be achieved.",
author = "A. Mitev and Marefat, {Michael Mahmoud} and D. Ma and Meiling Wang",
year = "2008",
doi = "10.1049/iet-cds:20070185",
language = "English (US)",
volume = "2",
pages = "16--22",
journal = "IET Circuits, Devices and Systems",
issn = "1751-858X",
publisher = "Institution of Engineering and Technology",
number = "1",

}

TY - JOUR

T1 - Parameter reduction for variability analysis by slice inverse regression method

AU - Mitev, A.

AU - Marefat, Michael Mahmoud

AU - Ma, D.

AU - Wang, Meiling

PY - 2008

Y1 - 2008

N2 - With semiconductor fabrication technologies that have scaled below 100nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation integrated circuit (IC) design. One of the biggest challenges is the enormous number of process-variation-related parameters. These parameters represent numerous local and global variations and pose a heavy burden in today's chip verification and design processes. A new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance is proposed. The new approach creates an effective reduction subspace and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which variability analysis is processed. Thus, the computational cost because of the number of variations is greatly reduced. Experimental results show that by using the new method, 20-50 parameter reduction with only <5 error on average can be achieved.

AB - With semiconductor fabrication technologies that have scaled below 100nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation integrated circuit (IC) design. One of the biggest challenges is the enormous number of process-variation-related parameters. These parameters represent numerous local and global variations and pose a heavy burden in today's chip verification and design processes. A new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance is proposed. The new approach creates an effective reduction subspace and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which variability analysis is processed. Thus, the computational cost because of the number of variations is greatly reduced. Experimental results show that by using the new method, 20-50 parameter reduction with only <5 error on average can be achieved.

UR - http://www.scopus.com/inward/record.url?scp=40349102095&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=40349102095&partnerID=8YFLogxK

U2 - 10.1049/iet-cds:20070185

DO - 10.1049/iet-cds:20070185

M3 - Article

AN - SCOPUS:40349102095

VL - 2

SP - 16

EP - 22

JO - IET Circuits, Devices and Systems

JF - IET Circuits, Devices and Systems

SN - 1751-858X

IS - 1

ER -