With semiconductor fabrication technologies that have scaled below 100nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation integrated circuit (IC) design. One of the biggest challenges is the enormous number of process-variation-related parameters. These parameters represent numerous local and global variations and pose a heavy burden in today's chip verification and design processes. A new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance is proposed. The new approach creates an effective reduction subspace and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which variability analysis is processed. Thus, the computational cost because of the number of variations is greatly reduced. Experimental results show that by using the new method, 20-50 parameter reduction with only <5 error on average can be achieved.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Control and Systems Engineering