With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation IC design. One of the biggest challenges is the enormous number of process variation related parameters. These parameters represent numerous local and global variations, and pose a heavy burden in today's chip verification and design. This paper proposes a new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance. The new approach creates an effective reduction subspace (ERS) and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which we process variability analysis. Thus, the computational cost due to the number of variations is greatly reduced. Experimental results show that by using new method we can achieve 20% to 50% parameter reduction with only less than 8% error on average.