Partial bitstream 2-D core relocation for reconfigurable architectures

Chad Rossmeissl, Adarsha Sreeramareddy, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Field Programmable Gate Arrays (FPGAs) potentially offer enhanced reliability, recovery from failures through partial and dynamic reconfigurations, and eliminate the need for redundant hardware typically used in faulttolerant systems. Our earlier work on scalable self-configurable architectures for reusable space systems (SCARS) describes a partial reconfiguration based self-healing architecture. The implementation of this architecture with the currently available industry tools has taught us a few valuable lessons. Generating the partially reconfigurable cores has acute restrictions that limit our ability to relocate the cores to other regions of the FPGA leading to poor area utilization. State of the art relocation approaches in the academia employ complex relocation management mechanisms which prohibit these solutions to operate at run time. In this paper, we propose a methodology for run-time 2-D core relocation to overcome the above issues. We show that our approach increases reconfiguration area utilization by 36% and reduces partial bitstream storage memory usage by 91% when compared to our base implementation. Conventional solutions restrict a given functionality to be partially reconfigured in a predetermined area. This technology enables the designer to move any core to anywhere on the FPGA fabric providing more resource availability when recovering from failure.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009
Pages98-105
Number of pages8
DOIs
StatePublished - Dec 1 2009
Event2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009 - San Francisco, CA, United States
Duration: Jul 29 2009Aug 1 2009

Publication series

NameProceedings - 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009

Other

Other2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009
CountryUnited States
CitySan Francisco, CA
Period7/29/098/1/09

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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    Rossmeissl, C., Sreeramareddy, A., & Akoglu, A. (2009). Partial bitstream 2-D core relocation for reconfigurable architectures. In Proceedings - 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009 (pp. 98-105). [5325465] (Proceedings - 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009). https://doi.org/10.1109/AHS.2009.41