Abstract
Low-density parity check (LDPC) codes are an attractive error correction scheme for ensuring data integrity in new generation of NAND flash memories. A quick assessment of the iterative decoders for LDPC codes reveals a wide range of varying complexities. The simple Bit-Flipping (BF) and binary-message-passing algorithms such as the Gallager A/B algorithms occupy one end of the spectrum, while Belief Propagation (BP) and A Posteriori Probability (APP) decoders lie at the other end. The gamut of existing decoders filling the intermediate space can simply be understood as the implementation of BP (and its variants, such as the min-sum algorithm) at different levels of message precision. Decoders with low-precision messages are desirable because of their low complexity and power efficiency, but in such decoders it is highly nontrivial to prevent performance degradation known to as error floor and to guarantee fast convergence to a codeword. In this paper we present our results on a new class of low-complexity iterative decoders for flash memory channels. They involve two main innovations: global computation and randomness. Our decoding algorithm, Probabilistic Gradient Descent Bit-Flipping (PGDBF) is motivated by the analogy between Tanner graphs and the graphical models used in statistical mechanics, and prescribe a rule for flipping a bit based on the so-called energy function and a binary random sequence associated to that bit. Energy function is computationally simple, but involves all the bits. We present the PGDBF algorithm analysis, explain how it benefits from global computation and randomness, and present the hardware synthesis results as well as comparisons with the state-of-the-art decoders.
| Original language | English (US) |
|---|---|
| Title of host publication | 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Volume | 2018-May |
| ISBN (Electronic) | 9781538648810 |
| DOIs | |
| State | Published - Apr 26 2018 |
| Event | 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: May 27 2018 → May 30 2018 |
Other
| Other | 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 |
|---|---|
| Country | Italy |
| City | Florence |
| Period | 5/27/18 → 5/30/18 |
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Keywords
- high decoding throughput
- low-complexity FPGA implementation
- Low-Density Parity-Check
- NAND Flash Memory
- Probabilistic Gradient Descent Bit Flipping
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels. / Ghaffari, Fakhreddine; Vasic, Bane V.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Vol. 2018-May Institute of Electrical and Electronics Engineers Inc., 2018. 8351713.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels
AU - Ghaffari, Fakhreddine
AU - Vasic, Bane V
PY - 2018/4/26
Y1 - 2018/4/26
N2 - Low-density parity check (LDPC) codes are an attractive error correction scheme for ensuring data integrity in new generation of NAND flash memories. A quick assessment of the iterative decoders for LDPC codes reveals a wide range of varying complexities. The simple Bit-Flipping (BF) and binary-message-passing algorithms such as the Gallager A/B algorithms occupy one end of the spectrum, while Belief Propagation (BP) and A Posteriori Probability (APP) decoders lie at the other end. The gamut of existing decoders filling the intermediate space can simply be understood as the implementation of BP (and its variants, such as the min-sum algorithm) at different levels of message precision. Decoders with low-precision messages are desirable because of their low complexity and power efficiency, but in such decoders it is highly nontrivial to prevent performance degradation known to as error floor and to guarantee fast convergence to a codeword. In this paper we present our results on a new class of low-complexity iterative decoders for flash memory channels. They involve two main innovations: global computation and randomness. Our decoding algorithm, Probabilistic Gradient Descent Bit-Flipping (PGDBF) is motivated by the analogy between Tanner graphs and the graphical models used in statistical mechanics, and prescribe a rule for flipping a bit based on the so-called energy function and a binary random sequence associated to that bit. Energy function is computationally simple, but involves all the bits. We present the PGDBF algorithm analysis, explain how it benefits from global computation and randomness, and present the hardware synthesis results as well as comparisons with the state-of-the-art decoders.
AB - Low-density parity check (LDPC) codes are an attractive error correction scheme for ensuring data integrity in new generation of NAND flash memories. A quick assessment of the iterative decoders for LDPC codes reveals a wide range of varying complexities. The simple Bit-Flipping (BF) and binary-message-passing algorithms such as the Gallager A/B algorithms occupy one end of the spectrum, while Belief Propagation (BP) and A Posteriori Probability (APP) decoders lie at the other end. The gamut of existing decoders filling the intermediate space can simply be understood as the implementation of BP (and its variants, such as the min-sum algorithm) at different levels of message precision. Decoders with low-precision messages are desirable because of their low complexity and power efficiency, but in such decoders it is highly nontrivial to prevent performance degradation known to as error floor and to guarantee fast convergence to a codeword. In this paper we present our results on a new class of low-complexity iterative decoders for flash memory channels. They involve two main innovations: global computation and randomness. Our decoding algorithm, Probabilistic Gradient Descent Bit-Flipping (PGDBF) is motivated by the analogy between Tanner graphs and the graphical models used in statistical mechanics, and prescribe a rule for flipping a bit based on the so-called energy function and a binary random sequence associated to that bit. Energy function is computationally simple, but involves all the bits. We present the PGDBF algorithm analysis, explain how it benefits from global computation and randomness, and present the hardware synthesis results as well as comparisons with the state-of-the-art decoders.
KW - high decoding throughput
KW - low-complexity FPGA implementation
KW - Low-Density Parity-Check
KW - NAND Flash Memory
KW - Probabilistic Gradient Descent Bit Flipping
UR - http://www.scopus.com/inward/record.url?scp=85057121896&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85057121896&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2018.8351713
DO - 10.1109/ISCAS.2018.8351713
M3 - Conference contribution
AN - SCOPUS:85057121896
VL - 2018-May
BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -