QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

Dominic Ditomaso, Avinash Kodi, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Scopus citations

Abstract

Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and will result in a significant increase in faults (both permanent and transient) and hardware failures. In this paper, we propose QORE - a fault tolerant NoC architecture with Quad-Function Channel (QFC) buffers. The use of QFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by allowing the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, QFC buffers reduce router power and improve performance by eliminating in-router buffering. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by 1.3× and throughput by 2.3× when compared to state-of-the art fault tolerant NoCs designs such as Ariadne and Vicis. Moreover, using Synopsys Design Compiler, we also show that network power in QORE is reduced by 21% with minimal control overhead.

Original languageEnglish (US)
Title of host publication20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
PublisherIEEE Computer Society
Pages320-331
Number of pages12
ISBN (Print)9781479930975
DOIs
StatePublished - Jan 1 2014
Event20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 - Orlando, FL, United States
Duration: Feb 15 2014Feb 19 2014

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
CountryUnited States
CityOrlando, FL
Period2/15/142/19/14

ASJC Scopus subject areas

  • Hardware and Architecture

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    Ditomaso, D., Kodi, A., & Louri, A. (2014). QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 (pp. 320-331). [6835942] (Proceedings - International Symposium on High-Performance Computer Architecture). IEEE Computer Society. https://doi.org/10.1109/HPCA.2014.6835942