Realizable parasitic reduction for distributed interconnects using matrix pencil technique

Janet Wang, Prashant Saxena, Omar Hafiz, Xing Wang

Research output: Contribution to conferencePaper

Abstract

With the increasing design complexity, integrating realizable reduction techniques into design flows has shown more advantages than the traditional model order reduction methods. In this paper, we propose a realizable parasitic reduction method for RLGC distributed interconnects . The proposed method obatains a reduced order model based on a modified matrix pencil method. By using a set of analytic formulas, this method provides synthesied RLGC elements. This new model is applied to power grid and antena circuits involving triangular input waveforms, lossy transmission lines and discontinuities of interconnects. The results show better reduction ratio than the standard macromodels and good accuracy compared with the theoretical values.

Original languageEnglish (US)
Pages781-786
Number of pages6
StatePublished - Jun 1 2004
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: Jan 27 2004Jan 30 2004

Other

OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CountryJapan
CityYokohama
Period1/27/041/30/04

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Wang, J., Saxena, P., Hafiz, O., & Wang, X. (2004). Realizable parasitic reduction for distributed interconnects using matrix pencil technique. 781-786. Paper presented at Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.