A full-wafer, 10,580 × 10,560 pixel (95 × 95 mm) CCD was designed and tested at Semiconductor Technology Associates (STA) with 9 μm. square pixels and 16 outputs. The chip was successfully fabricated in 2006 at DALSA and some performance results are presented here. This program was funded by the Office of Naval Research through a Small Business Innovation in Research (SBIR) program requested by the U.S. Naval Observatory for its next generation astrometric sky survey programs. Using Leach electronics, low read-noise output of the 111 million pixels requires 16 seconds at 0.9 MHz. Alternative electronics developed at STA allow readout at 20 MHz. Some modifications of the design to include anti-blooming features, a larger number of outputs, and use of p-channel material for space applications are discussed.