Reconfigurable on-chip antenna arrays for multi-chip RF data transmission

Sungjong Yoo, Kathleen L Melde

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multicore computer architectures with upwards of 100 processor cores on a single chip promise unprecedented enhancement of computational performance. There are many key performance issues in computing on multicore systems that do not exist in single core computers or even computers with a few cores. Maximum computational performance, such as ideal load balancing and low latency, can only be achieved with efficient data transfers between cores. The full promise of multicore systems cannot be achieved unless efficient (both in energy and time) communications between cores is realized. In an multicore computer architecture with hundreds cores, physical connections will severely restrict system performance due to slowed data transfer, excessive power consumption and required redundancy for broken data links.

Original languageEnglish (US)
Title of host publication2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages35
Number of pages1
ISBN (Print)9781479937462
DOIs
StatePublished - Nov 12 2014
Event2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Memphis, United States
Duration: Jul 6 2014Jul 11 2014

Other

Other2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014
CountryUnited States
CityMemphis
Period7/6/147/11/14

Fingerprint

Computer architecture
Data transfer
Antenna arrays
Data communication systems
Resource allocation
Redundancy
Electric power utilization
Communication

ASJC Scopus subject areas

  • Artificial Intelligence
  • Human-Computer Interaction
  • Electrical and Electronic Engineering

Cite this

Yoo, S., & Melde, K. L. (2014). Reconfigurable on-chip antenna arrays for multi-chip RF data transmission. In 2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings (pp. 35). [6955417] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/USNC-URSI.2014.6955417

Reconfigurable on-chip antenna arrays for multi-chip RF data transmission. / Yoo, Sungjong; Melde, Kathleen L.

2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2014. p. 35 6955417.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoo, S & Melde, KL 2014, Reconfigurable on-chip antenna arrays for multi-chip RF data transmission. in 2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings., 6955417, Institute of Electrical and Electronics Engineers Inc., pp. 35, 2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014, Memphis, United States, 7/6/14. https://doi.org/10.1109/USNC-URSI.2014.6955417
Yoo S, Melde KL. Reconfigurable on-chip antenna arrays for multi-chip RF data transmission. In 2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2014. p. 35. 6955417 https://doi.org/10.1109/USNC-URSI.2014.6955417
Yoo, Sungjong ; Melde, Kathleen L. / Reconfigurable on-chip antenna arrays for multi-chip RF data transmission. 2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 35
@inproceedings{d1f6ce1439294c37a060ea21d1bb95f7,
title = "Reconfigurable on-chip antenna arrays for multi-chip RF data transmission",
abstract = "Multicore computer architectures with upwards of 100 processor cores on a single chip promise unprecedented enhancement of computational performance. There are many key performance issues in computing on multicore systems that do not exist in single core computers or even computers with a few cores. Maximum computational performance, such as ideal load balancing and low latency, can only be achieved with efficient data transfers between cores. The full promise of multicore systems cannot be achieved unless efficient (both in energy and time) communications between cores is realized. In an multicore computer architecture with hundreds cores, physical connections will severely restrict system performance due to slowed data transfer, excessive power consumption and required redundancy for broken data links.",
author = "Sungjong Yoo and Melde, {Kathleen L}",
year = "2014",
month = "11",
day = "12",
doi = "10.1109/USNC-URSI.2014.6955417",
language = "English (US)",
isbn = "9781479937462",
pages = "35",
booktitle = "2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Reconfigurable on-chip antenna arrays for multi-chip RF data transmission

AU - Yoo, Sungjong

AU - Melde, Kathleen L

PY - 2014/11/12

Y1 - 2014/11/12

N2 - Multicore computer architectures with upwards of 100 processor cores on a single chip promise unprecedented enhancement of computational performance. There are many key performance issues in computing on multicore systems that do not exist in single core computers or even computers with a few cores. Maximum computational performance, such as ideal load balancing and low latency, can only be achieved with efficient data transfers between cores. The full promise of multicore systems cannot be achieved unless efficient (both in energy and time) communications between cores is realized. In an multicore computer architecture with hundreds cores, physical connections will severely restrict system performance due to slowed data transfer, excessive power consumption and required redundancy for broken data links.

AB - Multicore computer architectures with upwards of 100 processor cores on a single chip promise unprecedented enhancement of computational performance. There are many key performance issues in computing on multicore systems that do not exist in single core computers or even computers with a few cores. Maximum computational performance, such as ideal load balancing and low latency, can only be achieved with efficient data transfers between cores. The full promise of multicore systems cannot be achieved unless efficient (both in energy and time) communications between cores is realized. In an multicore computer architecture with hundreds cores, physical connections will severely restrict system performance due to slowed data transfer, excessive power consumption and required redundancy for broken data links.

UR - http://www.scopus.com/inward/record.url?scp=84916226791&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84916226791&partnerID=8YFLogxK

U2 - 10.1109/USNC-URSI.2014.6955417

DO - 10.1109/USNC-URSI.2014.6955417

M3 - Conference contribution

SN - 9781479937462

SP - 35

BT - 2014 USNC-URSI Radio Science Meeting (Joint with AP-S Symposium), USNC-URSI 2014 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -