Reliability of memories built from unreliable components under data-dependent gate failures

Srdan Brkic, Predrag Ivaniš, Bane V Vasic

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

In this letter, we investigate fault-tolerance of memories built from unreliable cells. In order to increase thememory reliability, information is encoded by a low-density paritycheck (LDPC) code, and then stored. The memory content is updated periodically by the bit-flipping decoder, built also from unreliable logic gates, whose failures are transient and datadependent. Based on the expander property of Tanner graph of LDPC codes, we prove that the proposed memory architecture can tolerate a fixed fraction of component failures and consequently preserve all the stored information, if code length tends to infinity.

Original languageEnglish (US)
Article number7312924
Pages (from-to)2098-2101
Number of pages4
JournalIEEE Communications Letters
Volume19
Issue number12
DOIs
StatePublished - Dec 1 2015

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Dependent Data
Data storage equipment
Memory architecture
Logic gates
Fault tolerance
Expander
Fault Tolerance
Infinity
Tend
Logic
Cell
Graph in graph theory

Keywords

  • Data-dependence
  • Faulty bit-flipping decoding
  • Low-density parity-check codes
  • Reliable memory architecture

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

Cite this

Reliability of memories built from unreliable components under data-dependent gate failures. / Brkic, Srdan; Ivaniš, Predrag; Vasic, Bane V.

In: IEEE Communications Letters, Vol. 19, No. 12, 7312924, 01.12.2015, p. 2098-2101.

Research output: Contribution to journalArticle

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