As electronic devices get smaller, reliability issues pose new challenges due to unknown underlying physics of failure mechanisms. This necessitates the development of new reliability analysis approaches related to nano-scale devices. One of the most important nano-devices is the transistor, and it is subject to various failure mechanisms. For such devices, dielectric breakdown is the most critical failure mode and has become a major barrier for reliable circuit design in nanoscale. Due to aggressive needs for the downscaling of transistors, dielectric films are made extremely thin. This has led to adopting high permittivity (k) dielectrics as an alternative to previously widely used SiO2, in recent years. Since most time-dependent dielectric breakdown test data on high-k bi-layer stacks significantly deviate from the Weibull trend, we propose a new approach to modeling the corresponding time-to-breakdown in this paper. A marked space-time self-exciting point process is employed in modeling defect generation rate. A simulation algorithm is used to generate defects within the dielectric space, and an optimization algorithm is developed to minimize the Kullback-Leibler divergence between the empirical distributions of real and simulated data to find the best set of the parameters and predict the total time-to-failure. The novelty of the presented approach lies in using a conditional intensity for trap generation in dielectrics that is a function of the times, locations and sizes of previous defects.