Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures

Dominic DiTomaso, Avinash Karanth Kodi, Ahmed Louri, Razvan Bunescu

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and will result in a significant increase in faults (both permanent and transient) and hardware failures. In this paper, we propose QORE - a fault tolerant NoC architecture with Multi-Function Channel (MFC) buffers. The use of MFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by allowing the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, MFC buffers reduce router power and improve performance by eliminating in-router buffering. We utilize a machine learning technique in our link controllers to predict the direction of traffic flow in order to more efficiently reverse links. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by 1.3x and throughput by 2.3x when compared to state-of-the art fault tolerant NoCs designs such as Ariadne and Vicis. Moreover, using Synopsys Design Compiler, we also show that network power in QORE is reduced by 21 percent with minimal control overhead.

Original languageEnglish (US)
Article number7035011
Pages (from-to)3555-3568
Number of pages14
JournalIEEE Transactions on Computers
Volume64
Issue number12
DOIs
StatePublished - Dec 1 2015

Fingerprint

Buffer
Router
Routers
Fault
Fault-tolerant
Reverse
Infant Mortality
Soft Error
Controller
Controllers
Communication
Communication Channels
Fault tolerance
Traffic Flow
Fault Tolerance
Compiler
High Power
Percent
Power Consumption
Learning systems

Keywords

  • Buffer storage
  • Circuit faults
  • Fault tolerant systems
  • Logic gates
  • Routing
  • Transistors

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures. / DiTomaso, Dominic; Kodi, Avinash Karanth; Louri, Ahmed; Bunescu, Razvan.

In: IEEE Transactions on Computers, Vol. 64, No. 12, 7035011, 01.12.2015, p. 3555-3568.

Research output: Contribution to journalArticle

DiTomaso, Dominic ; Kodi, Avinash Karanth ; Louri, Ahmed ; Bunescu, Razvan. / Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures. In: IEEE Transactions on Computers. 2015 ; Vol. 64, No. 12. pp. 3555-3568.
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