Robust clock tree routing in the presence of process variations

Uday Padmanabhan, Meiling Wang, Jiang Hu

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock skew still limits postmanufacturing performance. Process-induced skew presents an ever-growing limitation for high-speed large-area clock networks. To achieve multigigahertz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. This paper proposes a statistical centering-based clock routing algorithm that is built upon deferred merging embedding that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by the following ways: 1) choosing the best center measure which is dynamically based on the first three moments of the skew distribution and 2) designing for all sink pairs in the subtrees simultaneously. In addition, a variation-aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate that the proposed method reduces the number of skew violations by 12%-37%.

Original languageEnglish (US)
Article number4527108
Pages (from-to)1385-1397
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume27
Issue number8
DOIs
StatePublished - Aug 2008

Fingerprint

Clocks
VLSI circuits
Routing algorithms
Merging
Topology
Networks (circuits)
Experiments

Keywords

  • Clock tree
  • Process variation
  • Robust routing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

Cite this

Robust clock tree routing in the presence of process variations. / Padmanabhan, Uday; Wang, Meiling; Hu, Jiang.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 8, 4527108, 08.2008, p. 1385-1397.

Research output: Contribution to journalArticle

@article{9b630dabd1924ede80612d0034efe2a0,
title = "Robust clock tree routing in the presence of process variations",
abstract = "Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock skew still limits postmanufacturing performance. Process-induced skew presents an ever-growing limitation for high-speed large-area clock networks. To achieve multigigahertz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. This paper proposes a statistical centering-based clock routing algorithm that is built upon deferred merging embedding that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by the following ways: 1) choosing the best center measure which is dynamically based on the first three moments of the skew distribution and 2) designing for all sink pairs in the subtrees simultaneously. In addition, a variation-aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate that the proposed method reduces the number of skew violations by 12{\%}-37{\%}.",
keywords = "Clock tree, Process variation, Robust routing",
author = "Uday Padmanabhan and Meiling Wang and Jiang Hu",
year = "2008",
month = "8",
doi = "10.1109/TCAD.2008.925776",
language = "English (US)",
volume = "27",
pages = "1385--1397",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Robust clock tree routing in the presence of process variations

AU - Padmanabhan, Uday

AU - Wang, Meiling

AU - Hu, Jiang

PY - 2008/8

Y1 - 2008/8

N2 - Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock skew still limits postmanufacturing performance. Process-induced skew presents an ever-growing limitation for high-speed large-area clock networks. To achieve multigigahertz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. This paper proposes a statistical centering-based clock routing algorithm that is built upon deferred merging embedding that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by the following ways: 1) choosing the best center measure which is dynamically based on the first three moments of the skew distribution and 2) designing for all sink pairs in the subtrees simultaneously. In addition, a variation-aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate that the proposed method reduces the number of skew violations by 12%-37%.

AB - Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock skew still limits postmanufacturing performance. Process-induced skew presents an ever-growing limitation for high-speed large-area clock networks. To achieve multigigahertz operation for high-end designs, clock networks must be constructed to tolerate variations in various interconnect parameters. This paper proposes a statistical centering-based clock routing algorithm that is built upon deferred merging embedding that greatly improves skew tolerance to interconnect variations. The algorithm achieves the improvement by the following ways: 1) choosing the best center measure which is dynamically based on the first three moments of the skew distribution and 2) designing for all sink pairs in the subtrees simultaneously. In addition, a variation-aware abstract topology generation algorithm is proposed in this paper. Experiments on benchmark circuits demonstrate that the proposed method reduces the number of skew violations by 12%-37%.

KW - Clock tree

KW - Process variation

KW - Robust routing

UR - http://www.scopus.com/inward/record.url?scp=47849104483&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=47849104483&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2008.925776

DO - 10.1109/TCAD.2008.925776

M3 - Article

VL - 27

SP - 1385

EP - 1397

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 8

M1 - 4527108

ER -