Abstract
Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.
Original language | English (US) |
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Pages (from-to) | 478-492 |
Number of pages | 15 |
Journal | International Journal of Parallel Programming |
Volume | 36 |
Issue number | 5 |
DOIs | |
State | Published - Oct 1 2008 |
Keywords
- Dynamically adaptable systems
- Embedded systems
- Hardware/software partitioning
- Warp processing
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Information Systems