Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.

Original languageEnglish (US)
Pages (from-to)478-492
Number of pages15
JournalInternational Journal of Parallel Programming
Volume36
Issue number5
DOIs
StatePublished - Oct 1 2008

Keywords

  • Dynamically adaptable systems
  • Embedded systems
  • Hardware/software partitioning
  • Warp processing

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Information Systems

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