Abstract
Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 478-492 |
| Number of pages | 15 |
| Journal | International Journal of Parallel Programming |
| Volume | 36 |
| Issue number | 5 |
| DOIs | |
| State | Published - Oct 2008 |
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Keywords
- Dynamically adaptable systems
- Embedded systems
- Hardware/software partitioning
- Warp processing
ASJC Scopus subject areas
- Software
- Information Systems
- Theoretical Computer Science
Cite this
Scalability and parallel execution of warp processing : Dynamic hardware/software partitioning. / Lysecky, Roman L.
In: International Journal of Parallel Programming, Vol. 36, No. 5, 10.2008, p. 478-492.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Scalability and parallel execution of warp processing
T2 - Dynamic hardware/software partitioning
AU - Lysecky, Roman L
PY - 2008/10
Y1 - 2008/10
N2 - Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.
AB - Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.
KW - Dynamically adaptable systems
KW - Embedded systems
KW - Hardware/software partitioning
KW - Warp processing
UR - http://www.scopus.com/inward/record.url?scp=52549086188&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=52549086188&partnerID=8YFLogxK
U2 - 10.1007/s10766-008-0079-0
DO - 10.1007/s10766-008-0079-0
M3 - Article
VL - 36
SP - 478
EP - 492
JO - International Journal of Parallel Programming
JF - International Journal of Parallel Programming
SN - 0885-7458
IS - 5
ER -