Scalability and parallel execution of warp processing

Dynamic hardware/software partitioning

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.

Original languageEnglish (US)
Pages (from-to)478-492
Number of pages15
JournalInternational Journal of Parallel Programming
Volume36
Issue number5
DOIs
StatePublished - Oct 2008

Fingerprint

Hardware/software Partitioning
Scalability
Hardware
Field Programmable Gate Array
Software
Field programmable gate arrays (FPGA)
High Performance
Processing
ARM processors
Embedded Processor
Embedded systems
Embedded Systems
Power System
Chip
kernel
Resources
Networks (circuits)
Demonstrate

Keywords

  • Dynamically adaptable systems
  • Embedded systems
  • Hardware/software partitioning
  • Warp processing

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Theoretical Computer Science

Cite this

@article{6cbb776df0c7483ea27421fa66ab4c53,
title = "Scalability and parallel execution of warp processing: Dynamic hardware/software partitioning",
abstract = "Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.",
keywords = "Dynamically adaptable systems, Embedded systems, Hardware/software partitioning, Warp processing",
author = "Lysecky, {Roman L}",
year = "2008",
month = "10",
doi = "10.1007/s10766-008-0079-0",
language = "English (US)",
volume = "36",
pages = "478--492",
journal = "International Journal of Parallel Programming",
issn = "0885-7458",
publisher = "Springer New York",
number = "5",

}

TY - JOUR

T1 - Scalability and parallel execution of warp processing

T2 - Dynamic hardware/software partitioning

AU - Lysecky, Roman L

PY - 2008/10

Y1 - 2008/10

N2 - Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.

AB - Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.

KW - Dynamically adaptable systems

KW - Embedded systems

KW - Hardware/software partitioning

KW - Warp processing

UR - http://www.scopus.com/inward/record.url?scp=52549086188&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=52549086188&partnerID=8YFLogxK

U2 - 10.1007/s10766-008-0079-0

DO - 10.1007/s10766-008-0079-0

M3 - Article

VL - 36

SP - 478

EP - 492

JO - International Journal of Parallel Programming

JF - International Journal of Parallel Programming

SN - 0885-7458

IS - 5

ER -