Self-configurable architecture for reusable with Accelerated Relocation Circuit (SCARS-ARC)

Adarsha Sreeramareddy, Ramachandra Kallam, Aravind R. Dasu, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Field Programmable Gate Arrays (FPGAs), with partial reconfiguration (PR) technology present an attractive option for creating reliable platforms that adapt to changes in user objectives over time and respond to hardware/software anomalies automatically with selfhealing action. Conventional solutions for partial reconfiguration based self-configurable architectures experience severe hardware limitations on ability to move any partially reconfigurable module to any available region of the reconfigurable fabric and ability to relocate the module quickly. In this study we adopt the hardwarebased partial bitstream relocation technique, Accelerated Relocation Circuit (ARC), into the FPGA based wirelessly networked self-configurable architecture that employs traditional module based partial reconfiguration strategy. We show that the integrated architecture allows flexibility for module relocation, reduces the off-chip communication overhead, and observes up to 17x speedup for module relocation over the traditional Xilinx hardware internal configuration access port wrapper (HWICAP) based implementation.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010
DOIs
StatePublished - 2010
Event2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010 - Atlanta, GA, United States
Duration: Apr 19 2010Apr 23 2010

Other

Other2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010
CountryUnited States
CityAtlanta, GA
Period4/19/104/23/10

Fingerprint

Relocation
Module
Reconfiguration
Networks (circuits)
Partial
Hardware
Field programmable gate arrays (FPGA)
Field Programmable Gate Array
Wrapper
Anomaly
Speedup
Chip
Flexibility
Architecture
Communication
Internal
Configuration
Software

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Software
  • Theoretical Computer Science

Cite this

Sreeramareddy, A., Kallam, R., Dasu, A. R., & Akoglu, A. (2010). Self-configurable architecture for reusable with Accelerated Relocation Circuit (SCARS-ARC). In Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010 [5470749] https://doi.org/10.1109/IPDPSW.2010.5470749

Self-configurable architecture for reusable with Accelerated Relocation Circuit (SCARS-ARC). / Sreeramareddy, Adarsha; Kallam, Ramachandra; Dasu, Aravind R.; Akoglu, Ali.

Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010. 2010. 5470749.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sreeramareddy, A, Kallam, R, Dasu, AR & Akoglu, A 2010, Self-configurable architecture for reusable with Accelerated Relocation Circuit (SCARS-ARC). in Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010., 5470749, 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010, Atlanta, GA, United States, 4/19/10. https://doi.org/10.1109/IPDPSW.2010.5470749
Sreeramareddy A, Kallam R, Dasu AR, Akoglu A. Self-configurable architecture for reusable with Accelerated Relocation Circuit (SCARS-ARC). In Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010. 2010. 5470749 https://doi.org/10.1109/IPDPSW.2010.5470749
Sreeramareddy, Adarsha ; Kallam, Ramachandra ; Dasu, Aravind R. ; Akoglu, Ali. / Self-configurable architecture for reusable with Accelerated Relocation Circuit (SCARS-ARC). Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010. 2010.
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