Serial concatenation of reed muller and LDPC codes with low error floor

Xin Xiao, Mona Nasseri, Bane V Vasic, Shu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we propose a concatenated coding scheme involving an outer Reed-Muller (RM) code and an inner Finite Field low-density parity check (LDPC) code of medium length and high rate. It lowers the error floor of inner Finite Field LDPC code. This concatenation scheme offers flexibility in design and it is easy to implement. In addition, the decoding works in a serial turbo manner and has no harmful trapping sets of size smaller than the minimum distance of the outer code. The simulation results indicate that the proposed serial concatenation can eliminate the dominant trapping sets of the inner Finite Field LDPC code.

Original languageEnglish (US)
Title of host publication55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages688-693
Number of pages6
Volume2018-January
ISBN (Electronic)9781538632666
DOIs
StatePublished - Jan 17 2018
Event55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017 - Monticello, United States
Duration: Oct 3 2017Oct 6 2017

Other

Other55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017
CountryUnited States
CityMonticello
Period10/3/1710/6/17

Fingerprint

Low-density Parity-check (LDPC) Codes
Concatenation
Decoding
Galois field
Trapping
Reed-Muller Codes
Minimum Distance
Eliminate
Coding
Flexibility
Simulation

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Signal Processing
  • Energy Engineering and Power Technology
  • Control and Optimization

Cite this

Xiao, X., Nasseri, M., Vasic, B. V., & Lin, S. (2018). Serial concatenation of reed muller and LDPC codes with low error floor. In 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017 (Vol. 2018-January, pp. 688-693). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ALLERTON.2017.8262804

Serial concatenation of reed muller and LDPC codes with low error floor. / Xiao, Xin; Nasseri, Mona; Vasic, Bane V; Lin, Shu.

55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 688-693.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Xiao, X, Nasseri, M, Vasic, BV & Lin, S 2018, Serial concatenation of reed muller and LDPC codes with low error floor. in 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 688-693, 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017, Monticello, United States, 10/3/17. https://doi.org/10.1109/ALLERTON.2017.8262804
Xiao X, Nasseri M, Vasic BV, Lin S. Serial concatenation of reed muller and LDPC codes with low error floor. In 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 688-693 https://doi.org/10.1109/ALLERTON.2017.8262804
Xiao, Xin ; Nasseri, Mona ; Vasic, Bane V ; Lin, Shu. / Serial concatenation of reed muller and LDPC codes with low error floor. 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 688-693
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