Single-chip, asynchronous echo canceller for high-speed data communication

Richard P. Mackey, Jeffrey J. Rodriguez, Jo Dale Carothers, Sarma B.K. Vrudhula

Research output: Contribution to journalConference articlepeer-review

Abstract

A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

Original languageEnglish (US)
Pages (from-to)181-184
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Dec 1 1995
EventProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
Duration: Sep 18 1995Sep 22 1995

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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