Single-chip, asynchronous echo canceller for high-speed data communication

Richard P. Mackey, Jeffrey J Rodriguez, Jo Dale Carothers, Sarma B K Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
PublisherIEEE
Pages181-184
Number of pages4
StatePublished - 1995
EventProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
Duration: Sep 18 1995Sep 22 1995

Other

OtherProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit
CityAustin, TX, USA
Period9/18/959/22/95

Fingerprint

FIR filters
Sampling
Networks (circuits)
Communication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Mackey, R. P., Rodriguez, J. J., Carothers, J. D., & Vrudhula, S. B. K. (1995). Single-chip, asynchronous echo canceller for high-speed data communication. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 181-184). IEEE.

Single-chip, asynchronous echo canceller for high-speed data communication. / Mackey, Richard P.; Rodriguez, Jeffrey J; Carothers, Jo Dale; Vrudhula, Sarma B K.

Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE, 1995. p. 181-184.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mackey, RP, Rodriguez, JJ, Carothers, JD & Vrudhula, SBK 1995, Single-chip, asynchronous echo canceller for high-speed data communication. in Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE, pp. 181-184, Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, Austin, TX, USA, 9/18/95.
Mackey RP, Rodriguez JJ, Carothers JD, Vrudhula SBK. Single-chip, asynchronous echo canceller for high-speed data communication. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE. 1995. p. 181-184
Mackey, Richard P. ; Rodriguez, Jeffrey J ; Carothers, Jo Dale ; Vrudhula, Sarma B K. / Single-chip, asynchronous echo canceller for high-speed data communication. Proceedings of the Annual IEEE International ASIC Conference and Exhibit. IEEE, 1995. pp. 181-184
@inproceedings{fbeed7514b30493a96f1881a0a6a290b,
title = "Single-chip, asynchronous echo canceller for high-speed data communication",
abstract = "A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.",
author = "Mackey, {Richard P.} and Rodriguez, {Jeffrey J} and Carothers, {Jo Dale} and Vrudhula, {Sarma B K}",
year = "1995",
language = "English (US)",
pages = "181--184",
booktitle = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",
publisher = "IEEE",

}

TY - GEN

T1 - Single-chip, asynchronous echo canceller for high-speed data communication

AU - Mackey, Richard P.

AU - Rodriguez, Jeffrey J

AU - Carothers, Jo Dale

AU - Vrudhula, Sarma B K

PY - 1995

Y1 - 1995

N2 - A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

AB - A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

UR - http://www.scopus.com/inward/record.url?scp=0029539521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029539521&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029539521

SP - 181

EP - 184

BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

PB - IEEE

ER -