Software fault tolerance using dynamically reconfigurable FPGAs

K. A. Kwiat, W. H. Debany, Salim A Hariri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An emerging class of Field-Programmable Gate Arrays (FPGAs) permits partial reconfiguration of the device without disturbing the rest of the array - even while the device is operating. Dynamic device reconfiguration allows novel approaches to the migration of algorithms from software to hardware. New simulation tools are required in order to fully exploit the FPGA's versatility. We demonstrate how FPGA cells can be programmed and reprogrammed to provide a virtual FPGA that is much larger than the physical FPGA. In the context of dependable computing, our FPGA-based approach shows promise of significant performance gains over traditional software-intensive approaches. We apply this capability to the enhancement of software fault tolerance.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages39-42
Number of pages4
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA
Duration: Mar 22 1996Mar 23 1996

Other

OtherProceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI
CityAmes, IA, USA
Period3/22/963/23/96

Fingerprint

Fault tolerance
Field programmable gate arrays (FPGA)
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kwiat, K. A., Debany, W. H., & Hariri, S. A. (1996). Software fault tolerance using dynamically reconfigurable FPGAs. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 39-42). IEEE.

Software fault tolerance using dynamically reconfigurable FPGAs. / Kwiat, K. A.; Debany, W. H.; Hariri, Salim A.

Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, 1996. p. 39-42.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kwiat, KA, Debany, WH & Hariri, SA 1996, Software fault tolerance using dynamically reconfigurable FPGAs. in Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, pp. 39-42, Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI, Ames, IA, USA, 3/22/96.
Kwiat KA, Debany WH, Hariri SA. Software fault tolerance using dynamically reconfigurable FPGAs. In Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE. 1996. p. 39-42
Kwiat, K. A. ; Debany, W. H. ; Hariri, Salim A. / Software fault tolerance using dynamically reconfigurable FPGAs. Proceedings of the IEEE Great Lakes Symposium on VLSI. IEEE, 1996. pp. 39-42
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