Speculative sequential consistency with little custom storage

Christopher Gniady, B. Falsafi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Abstract

This paper proposes SC++lite, a sequentially consistent system that relaxes memory order speculatively to bridge the performance gap among memory consistency models. Prior proposals to speculatively relax memory order require large custom on-chip storage to maintain a history of speculative processor and memory state while memory order is relaxed. SC++lite uses the memory hierarchy to store the speculative history, providing a scalable path for speculative SC systems across a wide range of applications and system latencies. We use cycle-accurate simulation of shared-memory multiprocessors to show that SC++lite can fully relax memory order while virtually obviating the need for custom on-chip storage. Moreover while demand for storage increases significantly with larger memory latencies, SC++lite's ability to relax memory order remains insensitive to memory latency. An SC++lite system can improve performance over a base SC system by 28% with only 2 KB of custom storage in a system with 16 processors. In contrast, speculative SC systems with custom storage require 51 KB of storage to improve performance by 31% over a base SC system.

Original languageEnglish (US)
Title of host publicationParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages179-188
Number of pages10
Volume2002-January
ISBN (Print)0769516203
DOIs
StatePublished - 2002
Externally publishedYes
EventInternational Conference on Parallel Architectures and Compilation Techniques, PACT 2002 - Charlottesville, United States
Duration: Sep 22 2002Sep 25 2002

Other

OtherInternational Conference on Parallel Architectures and Compilation Techniques, PACT 2002
CountryUnited States
CityCharlottesville
Period9/22/029/25/02

Fingerprint

Data storage equipment
Latency
Chip
Shared-memory multiprocessors
Memory Hierarchy
Cycle
Path
Range of data
Simulation

Keywords

  • Bridges
  • Computer architecture
  • Delay
  • Hardware
  • History
  • Laboratories
  • Microprocessors
  • Proposals
  • System-on-a-chip

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Theoretical Computer Science

Cite this

Gniady, C., & Falsafi, B. (2002). Speculative sequential consistency with little custom storage. In Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT (Vol. 2002-January, pp. 179-188). [1106016] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PACT.2002.1106016

Speculative sequential consistency with little custom storage. / Gniady, Christopher; Falsafi, B.

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 179-188 1106016.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gniady, C & Falsafi, B 2002, Speculative sequential consistency with little custom storage. in Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. vol. 2002-January, 1106016, Institute of Electrical and Electronics Engineers Inc., pp. 179-188, International Conference on Parallel Architectures and Compilation Techniques, PACT 2002, Charlottesville, United States, 9/22/02. https://doi.org/10.1109/PACT.2002.1106016
Gniady C, Falsafi B. Speculative sequential consistency with little custom storage. In Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. Vol. 2002-January. Institute of Electrical and Electronics Engineers Inc. 2002. p. 179-188. 1106016 https://doi.org/10.1109/PACT.2002.1106016
Gniady, Christopher ; Falsafi, B. / Speculative sequential consistency with little custom storage. Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. pp. 179-188
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