TY - JOUR
T1 - Stochastic multi-objective Pareto-optimization framework for fully automated ab initio network-on-chip design
AU - Kao, Tzyy Juin
AU - Fink, Wolfgang
PY - 2020/2
Y1 - 2020/2
N2 - With the advent of multi-core processors, network-on-chip design has been crucial in addressing network performances, such as bandwidth, power consumption, and communication delays when dealing with on-chip communication between the increasing number of processor cores. As the numbers of cores increase, network design becomes inherently more complex. Therefore, there is a critical need in soliciting computer aid in determining network configurations that afford optimal performance given multi-objectives, such as resource and design constraints. We have devised a stochastic multi-objective Pareto-optimization framework that fully automatically explores the space of possible network configurations to determine optimal network latencies, power consumption, and the corresponding link allocations, i.e., the actual network-on-chip design, ab initio with only the number of routers given. For a given number of routers, average network latency and power consumption as example performance objectives can be displayed in form of Pareto-optimal fronts, thus not only offering a powerful automatic network-on-chip design tool, but also affording trade-off studies for the chip designers.
AB - With the advent of multi-core processors, network-on-chip design has been crucial in addressing network performances, such as bandwidth, power consumption, and communication delays when dealing with on-chip communication between the increasing number of processor cores. As the numbers of cores increase, network design becomes inherently more complex. Therefore, there is a critical need in soliciting computer aid in determining network configurations that afford optimal performance given multi-objectives, such as resource and design constraints. We have devised a stochastic multi-objective Pareto-optimization framework that fully automatically explores the space of possible network configurations to determine optimal network latencies, power consumption, and the corresponding link allocations, i.e., the actual network-on-chip design, ab initio with only the number of routers given. For a given number of routers, average network latency and power consumption as example performance objectives can be displayed in form of Pareto-optimal fronts, thus not only offering a powerful automatic network-on-chip design tool, but also affording trade-off studies for the chip designers.
KW - Automated ab initio network-on-chip design
KW - BookSim2.0 and gem5
KW - Multi-objective stochastic Pareto-optimization
KW - Network latency
KW - Power consumption
UR - http://www.scopus.com/inward/record.url?scp=85076978297&partnerID=8YFLogxK
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U2 - 10.1016/j.sysarc.2019.101686
DO - 10.1016/j.sysarc.2019.101686
M3 - Article
AN - SCOPUS:85076978297
VL - 103
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
SN - 1383-7621
M1 - 101686
ER -