Stress and reliability analysis of electronic packages with ultra-thin chips

Sergey V Shkarayev, Sergey Savastiouk, Oleg Siniaguine

Research output: Contribution to journalArticle

14 Citations (Scopus)

Abstract

This research concerns itself with a stress and reliability analysis of electronic packages with ultra-thin chips based on the finite element method. The effect of chip and substrate thickness, substrate material, presence of underfill, dimensions, and shape of the bump on stress reduction is analyzed. Obtained results clearly show that chip thinning, when used with an appropriate design of the entire package, can significantly decrease stresses and stress intensity factors and improve the reliability of the package. The developed software provides an effective design tool to quantify the reliability, stresses, and deflections of a package with ultra-thin chips.

Original languageEnglish (US)
Pages (from-to)98-103
Number of pages6
JournalJournal of Electronic Packaging, Transactions of the ASME
Volume125
Issue number1
DOIs
StatePublished - 2003

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Reliability analysis
Stress analysis
Substrates
Stress intensity factors
Finite element method

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Mechanical Engineering

Cite this

Stress and reliability analysis of electronic packages with ultra-thin chips. / Shkarayev, Sergey V; Savastiouk, Sergey; Siniaguine, Oleg.

In: Journal of Electronic Packaging, Transactions of the ASME, Vol. 125, No. 1, 2003, p. 98-103.

Research output: Contribution to journalArticle

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