Surrogating circuit design solutions with robustness metrics

Jin Sun, Liang Xiao, Jiangshan Tian, He Zhou, Janet Roveda

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

With the increase in device variability, the performance uncertainty poses a daunting challenge to analog/mixed-signal circuit design. This situation requires a robust design approach to add large margins to the circuit and system-level specification to ensure correct operation and the overall yield. In this paper, we propose a new robust design approach by using norm metrics to quantify the robustness for both design parameters and performance uncertainty. In addition, we adopt a surrogating procedure to achieve robustness in design space and to reduce uncertainty in performance space. The end result of the proposed method is a Pareto-surface that provides the designer with trade-offs between design robustness and performance uncertainty. One advantage of this new approach is the ability to take into account the strong nonlinear relationship between performance and design parameters. Considering a set of highly nonlinear circuit performances, we demonstrate the effectiveness of this robust design framework on a fully CMOS operational amplifier circuit.

Original languageEnglish (US)
Pages (from-to)1-9
Number of pages9
JournalIntegration, the VLSI Journal
Volume52
DOIs
StatePublished - Jan 1 2016

Keywords

  • ElasticR method
  • Process variations
  • Robust design
  • Robustness metric
  • Surrogates

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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