Symbolic analysis of faulty logic circuits in the presence of correlated gate failures

Srdjan Brkic, Predrag Ivanis, Goran Djordjevic, Bane Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present a method for symbolic analysis of unreliable logic circuits in the presence of correlated and data-dependent gate failures, described by Markov chains. Presented probabilistic algorithm is used for the analysis of majority logic and XOR logic circuits.

Original languageEnglish (US)
Title of host publication2013 21st Telecommunications Forum Telfor, TELFOR 2013 - Proceedings of Papers
Pages369-372
Number of pages4
DOIs
StatePublished - 2013
Event2013 21st Telecommunications Forum Telfor, TELFOR 2013 - Belgrade, Serbia
Duration: Nov 26 2013Nov 28 2013

Publication series

Name2013 21st Telecommunications Forum Telfor, TELFOR 2013 - Proceedings of Papers

Other

Other2013 21st Telecommunications Forum Telfor, TELFOR 2013
CountrySerbia
CityBelgrade
Period11/26/1311/28/13

Keywords

  • Combinatorial circuits
  • Markov chains
  • fault-tolerance
  • symbolic analysis

ASJC Scopus subject areas

  • Computer Networks and Communications

Fingerprint Dive into the research topics of 'Symbolic analysis of faulty logic circuits in the presence of correlated gate failures'. Together they form a unique fingerprint.

  • Cite this

    Brkic, S., Ivanis, P., Djordjevic, G., & Vasic, B. (2013). Symbolic analysis of faulty logic circuits in the presence of correlated gate failures. In 2013 21st Telecommunications Forum Telfor, TELFOR 2013 - Proceedings of Papers (pp. 369-372). [6716246] (2013 21st Telecommunications Forum Telfor, TELFOR 2013 - Proceedings of Papers). https://doi.org/10.1109/TELFOR.2013.6716246