Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. This leads to the difficulty for CAD tools to successfully and optimally map a circuit into these devices. Instead of switching to resource-rich FPGAs, the designers could employ depopulation based clustering technique which underuses CLBs, hence improves routability by spreading the logic over the architecture. However, all depopulation based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven non-uniform depopulation based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. We adjust the capacity of the CLB based on the criticality of the logic block. Paper analyzes the effect of depopulation strategies on area and delay performance. Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28%. More importantly, TNDPack decreases critical path delay by 2.89%.