Techniques for improved testability in the IBM ES/9370 system

Robert F. Lusch, Endre F. Sarkany

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The authors discuss three techniques used in the IBM ES/9370 series of processors to improve the testability, and hence the quality levels, of card assemblies. First, they investigate the testing requirements and challenges presented by a nonvolatile static RAM and how they were met. Then they introduce a method which uses flush-through logic to provide improved access to array components. Next, the authors discuss how a compare circuit can be used to reduce I/O (input/output) requirements when testing an array. These algorithms were successfully implemented using Programming Language for Testing (PLT). Background information and a detailed methodology for each of the techniques are provided.

Original languageEnglish (US)
Title of host publication20 Int Test Conf 1989 ITC
Editors Anon
PublisherPubl by IEEE
Pages290-294
Number of pages5
ISBN (Print)0818689625
StatePublished - Dec 1 1989
Event20th International Test Conference 1989 (ITC) - Washington, DC, USA
Duration: Aug 29 1989Aug 31 1989

Publication series

Name20 Int Test Conf 1989 ITC

Other

Other20th International Test Conference 1989 (ITC)
CityWashington, DC, USA
Period8/29/898/31/89

ASJC Scopus subject areas

  • Engineering(all)

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