Techniques for reducing read latency of core bus wrappers

Roman L Lysecky, Frank Vahid, Tony D. Givargis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Today's system-on-a-chip designs consist of many cores, To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic separated from their wrapper. This separation may introduce extra read latency. Pre-fetching register data into register copies in the bus wrapper can reduce or eliminate this extra latency. In this paper, we introduce a technique for automatically designing a pre-fetch unit that satisfies user-imposed register-access constraints. The technique benefits from mapping the pre-fetching problem to the well-known real-time process scheduling problem. We then extend the technique to allow user-specified register interdependencies, using a Petri net model, resulting in even more efficient pre-fetch schedules.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages84-91
Number of pages8
DOIs
Publication statusPublished - 2000
Externally publishedYes
EventDesign, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000 - Paris, France
Duration: Mar 27 2000Mar 30 2000

Other

OtherDesign, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000
CountryFrance
CityParis
Period3/27/003/30/00

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Keywords

  • Bus wrapper
  • Cores
  • Design reuse
  • Intellectual property
  • Interfacing
  • On-chip bus
  • System-on-a-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lysecky, R. L., Vahid, F., & Givargis, T. D. (2000). Techniques for reducing read latency of core bus wrappers. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 84-91). [840021] https://doi.org/10.1109/DATE.2000.840021