Thermomechanical Finite Element Analysis of Problems in Electronic Packaging Using the Disturbed State Concept

Part 2 - Verification and Application

C. Basaran, C. S. Desai, Tribikram Kundu

Research output: Contribution to journalArticle

26 Citations (Scopus)

Abstract

The finite element procedure with the unified disturbed state modeling concept presented in Part I, Basaran et al. (1998), is verified here with respect to laboratory test results for Pb40/Sn60 eutectic solder alloy. This solder alloy is a commonly used interconnection material for surface mount technology packages. It is demonstrated that the proposed procedure provides highly satisfactory correlation with the observed laboratory behavior of materials and with test results for a chip-substrate system simulated in the laboratory.

Original languageEnglish (US)
Pages (from-to)48-53
Number of pages6
JournalJournal of Electronic Packaging, Transactions of the ASME
Volume120
Issue number1
StatePublished - Mar 1998

Fingerprint

Electronics packaging
Finite element method
Soldering alloys
Surface mount technology
Eutectics
Substrates

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Mechanical Engineering

Cite this

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abstract = "The finite element procedure with the unified disturbed state modeling concept presented in Part I, Basaran et al. (1998), is verified here with respect to laboratory test results for Pb40/Sn60 eutectic solder alloy. This solder alloy is a commonly used interconnection material for surface mount technology packages. It is demonstrated that the proposed procedure provides highly satisfactory correlation with the observed laboratory behavior of materials and with test results for a chip-substrate system simulated in the laboratory.",
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