Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration

Randy W. Morris, Avinash Karanth Kodi, Ahmed Louri, Ralph D. Whaley

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore and many-core architectures. Two disruptive technologies on the horizon are nanophotonic interconnects (NIs) and 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing a reasonable performance-per-watt in the future. Three-dimensional stacking can reduce the interconnect distance and increase the bandwidth density by incorporating multiple communication layers. In this paper, we propose an architecture that combines NIs and 3D stacking to design an energy-efficient and reconfigurable NoC. We quantitatively compare the hardware complexity of the proposed topology to other nanophotonic networks in terms of hop count, network diameter, radix, and photonic parameters. To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations. For 64-core reconfigured network, our simulation results indicate that the execution time can be reduced up to 25 percent for Splash-2, PARSEC, and SPEC CPU2006 benchmarks. Moreover, for a 256 - core version of the proposed architecture, our simulation results indicate a throughput improvement of more than 25 percent and energy savings of 23 percent on synthetic traffic when compared to competitive on-chip electrical and optical networks.

Original languageEnglish (US)
Article number6256662
Pages (from-to)243-255
Number of pages13
JournalIEEE Transactions on Computers
Volume63
Issue number1
DOIs
StatePublished - Jan 2014

Fingerprint

Nanophotonics
Interconnect
Reconfiguration
Stacking
Percent
Three-dimensional
Bandwidth
Chip
Throughput
Traffic
Impetus
Electrical Networks
Many-core
Network Simulation
Optical Networks
Energy Saving
Fiber optic networks
Energy Efficiency
Photonics
Energy Efficient

Keywords

  • 3D stacking
  • CMP
  • Nanophotonics
  • NoC
  • Reconfigurable

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration. / Morris, Randy W.; Kodi, Avinash Karanth; Louri, Ahmed; Whaley, Ralph D.

In: IEEE Transactions on Computers, Vol. 63, No. 1, 6256662, 01.2014, p. 243-255.

Research output: Contribution to journalArticle

Morris, Randy W. ; Kodi, Avinash Karanth ; Louri, Ahmed ; Whaley, Ralph D. / Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration. In: IEEE Transactions on Computers. 2014 ; Vol. 63, No. 1. pp. 243-255.
@article{abb83a3ed8a44c1a8d9de65b526435d8,
title = "Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration",
abstract = "As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore and many-core architectures. Two disruptive technologies on the horizon are nanophotonic interconnects (NIs) and 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing a reasonable performance-per-watt in the future. Three-dimensional stacking can reduce the interconnect distance and increase the bandwidth density by incorporating multiple communication layers. In this paper, we propose an architecture that combines NIs and 3D stacking to design an energy-efficient and reconfigurable NoC. We quantitatively compare the hardware complexity of the proposed topology to other nanophotonic networks in terms of hop count, network diameter, radix, and photonic parameters. To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations. For 64-core reconfigured network, our simulation results indicate that the execution time can be reduced up to 25 percent for Splash-2, PARSEC, and SPEC CPU2006 benchmarks. Moreover, for a 256 - core version of the proposed architecture, our simulation results indicate a throughput improvement of more than 25 percent and energy savings of 23 percent on synthetic traffic when compared to competitive on-chip electrical and optical networks.",
keywords = "3D stacking, CMP, Nanophotonics, NoC, Reconfigurable",
author = "Morris, {Randy W.} and Kodi, {Avinash Karanth} and Ahmed Louri and Whaley, {Ralph D.}",
year = "2014",
month = "1",
doi = "10.1109/TC.2012.183",
language = "English (US)",
volume = "63",
pages = "243--255",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "1",

}

TY - JOUR

T1 - Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration

AU - Morris, Randy W.

AU - Kodi, Avinash Karanth

AU - Louri, Ahmed

AU - Whaley, Ralph D.

PY - 2014/1

Y1 - 2014/1

N2 - As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore and many-core architectures. Two disruptive technologies on the horizon are nanophotonic interconnects (NIs) and 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing a reasonable performance-per-watt in the future. Three-dimensional stacking can reduce the interconnect distance and increase the bandwidth density by incorporating multiple communication layers. In this paper, we propose an architecture that combines NIs and 3D stacking to design an energy-efficient and reconfigurable NoC. We quantitatively compare the hardware complexity of the proposed topology to other nanophotonic networks in terms of hop count, network diameter, radix, and photonic parameters. To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations. For 64-core reconfigured network, our simulation results indicate that the execution time can be reduced up to 25 percent for Splash-2, PARSEC, and SPEC CPU2006 benchmarks. Moreover, for a 256 - core version of the proposed architecture, our simulation results indicate a throughput improvement of more than 25 percent and energy savings of 23 percent on synthetic traffic when compared to competitive on-chip electrical and optical networks.

AB - As throughput, scalability, and energy efficiency in network-on-chips (NoCs) are becoming critical, there is a growing impetus to explore emerging technologies for implementing NoCs in future multicore and many-core architectures. Two disruptive technologies on the horizon are nanophotonic interconnects (NIs) and 3D stacking. NIs can deliver high on-chip bandwidth while delivering low energy/bit, thereby providing a reasonable performance-per-watt in the future. Three-dimensional stacking can reduce the interconnect distance and increase the bandwidth density by incorporating multiple communication layers. In this paper, we propose an architecture that combines NIs and 3D stacking to design an energy-efficient and reconfigurable NoC. We quantitatively compare the hardware complexity of the proposed topology to other nanophotonic networks in terms of hop count, network diameter, radix, and photonic parameters. To maximize performance, we also propose an efficient reconfiguration algorithm that dynamically reallocates channel bandwidth by adapting to traffic fluctuations. For 64-core reconfigured network, our simulation results indicate that the execution time can be reduced up to 25 percent for Splash-2, PARSEC, and SPEC CPU2006 benchmarks. Moreover, for a 256 - core version of the proposed architecture, our simulation results indicate a throughput improvement of more than 25 percent and energy savings of 23 percent on synthetic traffic when compared to competitive on-chip electrical and optical networks.

KW - 3D stacking

KW - CMP

KW - Nanophotonics

KW - NoC

KW - Reconfigurable

UR - http://www.scopus.com/inward/record.url?scp=84890532746&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84890532746&partnerID=8YFLogxK

U2 - 10.1109/TC.2012.183

DO - 10.1109/TC.2012.183

M3 - Article

AN - SCOPUS:84890532746

VL - 63

SP - 243

EP - 255

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 1

M1 - 6256662

ER -