Timing-driven nonuniform depopulation-based clustering

Hanyu Liu, Ali Akoglu

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAsbut have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

Original languageEnglish (US)
Article number158602
JournalInternational Journal of Reconfigurable Computing
Volume2010
DOIs
StatePublished - 2010

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Field programmable gate arrays (FPGA)
Clustering algorithms
Costs
Computer aided design
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Timing-driven nonuniform depopulation-based clustering. / Liu, Hanyu; Akoglu, Ali.

In: International Journal of Reconfigurable Computing, Vol. 2010, 158602, 2010.

Research output: Contribution to journalArticle

@article{fe767b3891b94e46973a0f23bd2401c0,
title = "Timing-driven nonuniform depopulation-based clustering",
abstract = "Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAsbut have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07{\%} while increasing the number of CLBs by 13.28{\%} compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89{\%}.",
author = "Hanyu Liu and Ali Akoglu",
year = "2010",
doi = "10.1155/2010/158602",
language = "English (US)",
volume = "2010",
journal = "International Journal of Reconfigurable Computing",
issn = "1687-7195",
publisher = "Hindawi Publishing Corporation",

}

TY - JOUR

T1 - Timing-driven nonuniform depopulation-based clustering

AU - Liu, Hanyu

AU - Akoglu, Ali

PY - 2010

Y1 - 2010

N2 - Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAsbut have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

AB - Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAsbut have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

UR - http://www.scopus.com/inward/record.url?scp=78650795130&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78650795130&partnerID=8YFLogxK

U2 - 10.1155/2010/158602

DO - 10.1155/2010/158602

M3 - Article

AN - SCOPUS:78650795130

VL - 2010

JO - International Journal of Reconfigurable Computing

JF - International Journal of Reconfigurable Computing

SN - 1687-7195

M1 - 158602

ER -