Uncertainty modeling of gate delay considering multiple input switching

Satish Yanamanamanda, Jun Li, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

With the continual advancement in manufacturing technologies and the resultant process variations, delay variability is becoming increasingly significant. Statistical models have become mandatory to model the delay variability. It has also been experimentally proved that ignoring Multiple Input Switching and approximating it by Single Input Switching results in significant error. In this paper, we propose a new gate delay model that considers the impact of both process variations and multiple input switching. The proposed model uses an orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit's output response. The obtained analytical equation is used to evaluate the output delay distribution. Experimental results show that our approach gives a mean delay error less than 0.1% and a standard deviation error less than 2% when compared with Monte Carlo analysis.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages2457-2460
Number of pages4
DOIs
StatePublished - 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005

Other

OtherIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
CountryJapan
CityKobe
Period5/23/055/26/05

Fingerprint

Polynomials
Networks (circuits)
Uncertainty
Statistical Models

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yanamanamanda, S., Li, J., & Wang, M. (2005). Uncertainty modeling of gate delay considering multiple input switching. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 2457-2460). [1465123] https://doi.org/10.1109/ISCAS.2005.1465123

Uncertainty modeling of gate delay considering multiple input switching. / Yanamanamanda, Satish; Li, Jun; Wang, Meiling.

Proceedings - IEEE International Symposium on Circuits and Systems. 2005. p. 2457-2460 1465123.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yanamanamanda, S, Li, J & Wang, M 2005, Uncertainty modeling of gate delay considering multiple input switching. in Proceedings - IEEE International Symposium on Circuits and Systems., 1465123, pp. 2457-2460, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, Japan, 5/23/05. https://doi.org/10.1109/ISCAS.2005.1465123
Yanamanamanda S, Li J, Wang M. Uncertainty modeling of gate delay considering multiple input switching. In Proceedings - IEEE International Symposium on Circuits and Systems. 2005. p. 2457-2460. 1465123 https://doi.org/10.1109/ISCAS.2005.1465123
Yanamanamanda, Satish ; Li, Jun ; Wang, Meiling. / Uncertainty modeling of gate delay considering multiple input switching. Proceedings - IEEE International Symposium on Circuits and Systems. 2005. pp. 2457-2460
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