Uncertainty modeling of gate delay considering multiple input switching

Satish Yanamanamanda, Jun Li, Janet Wang

Research output: Contribution to journalConference article

5 Scopus citations

Abstract

With the continual advancement in manufacturing technologies and the resultant process variations, delay variability is becoming increasingly significant. Statistical models have become mandatory to model the delay variability. It has also been experimentally proved that ignoring Multiple Input Switching and approximating it by Single Input Switching results in significant error. In this paper, we propose a new gate delay model that considers the impact of both process variations and multiple input switching. The proposed model uses an orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit's output response. The obtained analytical equation is used to evaluate the output delay distribution. Experimental results show that our approach gives a mean delay error less than 0.1% and a standard deviation error less than 2% when compared with Monte Carlo analysis.

Original languageEnglish (US)
Article number1465123
Pages (from-to)2457-2460
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - Dec 1 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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