Unscheduling, unpredication, unspeculation: Reverse engineering Itanium executables

Noah Snavely, Saumya K Debray, Gregory Andrews

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

EPIC (Explicitly Parallel Instruction Computing) architectures, exemplified by the Intel Itanium, support a number of advanced architectural features, such as explicit instruction-level parallelism, instruction predication, and speculative loads from memory. However, compiler optimizations to take advantage of such architectural features can profoundly restructure the program's code, making it potentially difficult to reconstruct the original program logic from an optimized Itanium executable. This paper describes techniques to undo some of the effects of such optimizations and thereby improve the quality of reverse engineering such executables.

Original languageEnglish (US)
Title of host publicationProceedings - Working Conference on Reverse Engineering, WCRE
PublisherIEEE Computer Society
Pages4-13
Number of pages10
Volume2003-January
ISBN (Print)0769520278
DOIs
StatePublished - 2003
Event10th Working Conference on Reverse Engineering, WCRE 2003 - Victoria, Canada
Duration: Nov 13 2003Nov 16 2003

Other

Other10th Working Conference on Reverse Engineering, WCRE 2003
CountryCanada
CityVictoria
Period11/13/0311/16/03

Keywords

  • Computer aided instruction
  • Computer architecture
  • Computer science
  • Concurrent computing
  • Delay
  • Logic
  • Optimizing compilers
  • Parallel processing
  • Pipelines
  • Reverse engineering

ASJC Scopus subject areas

  • Software

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  • Cite this

    Snavely, N., Debray, S. K., & Andrews, G. (2003). Unscheduling, unpredication, unspeculation: Reverse engineering Itanium executables. In Proceedings - Working Conference on Reverse Engineering, WCRE (Vol. 2003-January, pp. 4-13). [1287232] IEEE Computer Society. https://doi.org/10.1109/WCRE.2003.1287232