WL-Emap: Wirelength prediction based technology mapping for FPGAs

Rodrigo Savage Chávez, Senthilkumar Thoravi Rajavel, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13% with a critical path delay overhead of 1.6% for the combinatorial MCNC benchmarks, and by 15.79% with a critical path delay overhead of 6.95% for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15% channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.

Original languageEnglish (US)
Title of host publicationSPL 2012 - 8th Southern Programmable Logic Conference
DOIs
StatePublished - 2012
Event8th Southern Programmable Logic Conference, SPL 2012 - Bento Goncalves, Brazil
Duration: Mar 20 2012Mar 23 2012

Other

Other8th Southern Programmable Logic Conference, SPL 2012
CountryBrazil
CityBento Goncalves
Period3/20/123/23/12

Fingerprint

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Critical Path
Cost functions
Placement
Cost Function
Prediction
Benchmark
Path Length
Shortest path
Routing
Clustering
Predict
Architecture

Keywords

  • FPGA
  • routability
  • technology mapping
  • wirelength prediction

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Applied Mathematics

Cite this

Chávez, R. S., Rajavel, S. T., & Akoglu, A. (2012). WL-Emap: Wirelength prediction based technology mapping for FPGAs. In SPL 2012 - 8th Southern Programmable Logic Conference [6211800] https://doi.org/10.1109/SPL.2012.6211800

WL-Emap : Wirelength prediction based technology mapping for FPGAs. / Chávez, Rodrigo Savage; Rajavel, Senthilkumar Thoravi; Akoglu, Ali.

SPL 2012 - 8th Southern Programmable Logic Conference. 2012. 6211800.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chávez, RS, Rajavel, ST & Akoglu, A 2012, WL-Emap: Wirelength prediction based technology mapping for FPGAs. in SPL 2012 - 8th Southern Programmable Logic Conference., 6211800, 8th Southern Programmable Logic Conference, SPL 2012, Bento Goncalves, Brazil, 3/20/12. https://doi.org/10.1109/SPL.2012.6211800
Chávez RS, Rajavel ST, Akoglu A. WL-Emap: Wirelength prediction based technology mapping for FPGAs. In SPL 2012 - 8th Southern Programmable Logic Conference. 2012. 6211800 https://doi.org/10.1109/SPL.2012.6211800
Chávez, Rodrigo Savage ; Rajavel, Senthilkumar Thoravi ; Akoglu, Ali. / WL-Emap : Wirelength prediction based technology mapping for FPGAs. SPL 2012 - 8th Southern Programmable Logic Conference. 2012.
@inproceedings{5e745e7f65f14a59ba45e2ec88b4d3c5,
title = "WL-Emap: Wirelength prediction based technology mapping for FPGAs",
abstract = "Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13{\%} with a critical path delay overhead of 1.6{\%} for the combinatorial MCNC benchmarks, and by 15.79{\%} with a critical path delay overhead of 6.95{\%} for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15{\%} channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.",
keywords = "FPGA, routability, technology mapping, wirelength prediction",
author = "Ch{\'a}vez, {Rodrigo Savage} and Rajavel, {Senthilkumar Thoravi} and Ali Akoglu",
year = "2012",
doi = "10.1109/SPL.2012.6211800",
language = "English (US)",
isbn = "9781467301862",
booktitle = "SPL 2012 - 8th Southern Programmable Logic Conference",

}

TY - GEN

T1 - WL-Emap

T2 - Wirelength prediction based technology mapping for FPGAs

AU - Chávez, Rodrigo Savage

AU - Rajavel, Senthilkumar Thoravi

AU - Akoglu, Ali

PY - 2012

Y1 - 2012

N2 - Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13% with a critical path delay overhead of 1.6% for the combinatorial MCNC benchmarks, and by 15.79% with a critical path delay overhead of 6.95% for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15% channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.

AB - Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13% with a critical path delay overhead of 1.6% for the combinatorial MCNC benchmarks, and by 15.79% with a critical path delay overhead of 6.95% for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15% channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.

KW - FPGA

KW - routability

KW - technology mapping

KW - wirelength prediction

UR - http://www.scopus.com/inward/record.url?scp=84863889193&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863889193&partnerID=8YFLogxK

U2 - 10.1109/SPL.2012.6211800

DO - 10.1109/SPL.2012.6211800

M3 - Conference contribution

AN - SCOPUS:84863889193

SN - 9781467301862

BT - SPL 2012 - 8th Southern Programmable Logic Conference

ER -