WL-Emap: Wirelength prediction based technology mapping for FPGAs

Rodrigo Savage Chávez, Senthilkumar Thoravi Rajavel, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13% with a critical path delay overhead of 1.6% for the combinatorial MCNC benchmarks, and by 15.79% with a critical path delay overhead of 6.95% for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15% channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.

Original languageEnglish (US)
Title of host publicationSPL 2012 - 8th Southern Programmable Logic Conference
DOIs
StatePublished - Jul 23 2012
Event8th Southern Programmable Logic Conference, SPL 2012 - Bento Goncalves, Brazil
Duration: Mar 20 2012Mar 23 2012

Publication series

NameSPL 2012 - 8th Southern Programmable Logic Conference

Other

Other8th Southern Programmable Logic Conference, SPL 2012
CountryBrazil
CityBento Goncalves
Period3/20/123/23/12

Keywords

  • FPGA
  • routability
  • technology mapping
  • wirelength prediction

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Applied Mathematics

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  • Cite this

    Chávez, R. S., Rajavel, S. T., & Akoglu, A. (2012). WL-Emap: Wirelength prediction based technology mapping for FPGAs. In SPL 2012 - 8th Southern Programmable Logic Conference [6211800] (SPL 2012 - 8th Southern Programmable Logic Conference). https://doi.org/10.1109/SPL.2012.6211800