Technology mapping is the first stage of the process of porting an application onto Field Programmable Gate Array (FPGA) architecture. This stage is highly critical as it sets the constraints of its successor stages of clustering, placement and routing. Intrinsic Shortest Path Length (ISPL) has been shown to accurately predict the post placement individual net length information for a given net list. In this study, we introduce the WL-Emap by replacing the switching activity based cut selection cost function of the Emap technology mapping algorithm with the wirelength factor based cost function. WL-Emap improves the channel width by 13.13% with a critical path delay overhead of 1.6% for the combinatorial MCNC benchmarks, and by 15.79% with a critical path delay overhead of 6.95% for all the 20 MCNC benchmarks using cluster size 4 over Emap. WL-Emap achieves over 15% channel width reduction performance with respect to the well-known technology mapping algorithms Flowmap, CutMap and WireMap.