Y-junction based addressing in optical symmetric multiprocessor networks

A. K. Kodi, A. Louri

Research output: Contribution to journalConference articlepeer-review

Abstract

An architecture based on scalable binary tree consisting of splitter/ combiners for address translation of optical symmetric multiprocessor (SMP), was proposed. The architecture featured optical time division multiplexing involving dual Y-junction splitter/combiner for backplane and on-board interconnections. The designs of 1x8 splitter with loss of 8.325dB for backplane and 1x4 splitters with losses of 6.53 dB for onboard interconnection were presented. The optical SMP network provides distinct performance and cost advantages over traditional electronic interconnect and other optical interconnection networks.

Original languageEnglish (US)
Pages (from-to)865-866
Number of pages2
JournalConference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS
Volume2
StatePublished - Dec 1 2001
Event14th Annual Meeting of the IEEE Lasers and Electro-Optics Society - San Diego, CA, United States
Duration: Nov 11 2001Nov 15 2001

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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